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Display ASIC Design Engineer

Qualcomm

This is a Contract position in Markham, ON posted March 14, 2020.

Qualcomm Technologies, Inc.

at http://www.qualcomm.com/about/businesses/qct Job Area Location Job Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives.

But this is just the beginning.

It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.

This is the Invention Age and this is where you come in.

Join the display design team as an ASIC Design Engineer where you will be part of a highly experienced multi-disciplinary and multi-site team that values collaboration, creativity, innovation and productivity.

You will interact with architects, designers, and verification engineers to help build next generation Display Processing Units (DPUs) that are key to delivering vivid and stunning visual experiences in the mobile, compute, automotive, and IoT markets.

The DPU is responsible for high performance and low power composition, processing and color management of image streams from the GPU, CPU, video decoder and camera.

It then formats, packetizes and synchronizes the composited image for display through display interfaces such as DSI and DisplayPort.

Your responsibilities will include: Develop micro-architecture and module specifications for key display processing blocks including those that interface with the SoC Analyze performance, area, power, and system cost tradeoffs for different micro-architecture implementations Implement modules and sub-systems in Verilog RTL Work closely with the design verification team to define verification methodology, test plans, reference and bus-functional models Help debug tests at the module, sub-system and SoC levels throughout the ASIC development cycle (pre and post-silicon) Work closely with implementation team to review synthesis results and reach static timing closure Interact with software teams to provide guidance on software driver implementation Make significant contributions to silicon debug and analysis Minimum Qualifications Bachelor’s degree in Science, Engineering, or related field.

Preferred Qualifications Bachelor’s degree in Electrical Engineering, Computer Science, or Computer Engineering.

6 months experience with architecture and design tools.

6 months experience with scripting tools and programming languages.

6 months experience with design verification methods.

Proficiency with Verilog/VHDL RTL design languages Experience with synthesis and timing closure Detail oriented with strong analytical and debugging skills Strong communication skills (written and verbal) Experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence Knowledge of bus interface protocols (AXI, AHB, APB) Education Requirements Required: Bachelor’s degree in Science, Engineering, or related field Preferred: Master’s, Computer Engineering and/or Electrical Engineering EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.