Video Codec Design Engineer

What you do at AMD changes everything

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Senior Member of Technical Staff Design Engineer

The Role:

We, the VCN (Video Codec Next) IP team, are based in Markham, ON, Canada. We focus on video codec IP development for AMD SOCs with leading ASIC technology. We are looking for a self-motivated, experienced (SMTS level) design engineer in the GTA area to complement our team to develop world class video solutions to the highest standards.

The Person:

You are expected to actively collaborate with various team members to understand design requirements, drive block level development, IP level bring-up, timing/area/performance trade-off throughout the design cycle. Solid technical skill, self-driven attitude, and excellent communication skill especially remotely are key factors to make you successful in this organization.

Key Responsibilities:

• Draft block level design requirement, micro-architecture spec.
• Perform block level modeling, RTL/HLS implementation.
• Define block programming model and interact with firmware/software team to bring-up functionality at IP and SOC level.
• Perform design metrics checks such as LINT, CDC, synthesis, static timing analysis and power analysis.
• Work with verification engineers to define test plan and functional coverage.
• Engage verification closure, including test debug, code coverage and functional coverage review and sign-off.
• Responsible for bug fixes, including engineering change order (ECO) implementation and verification through formal verification.

Preferred Experience:

• Minimum 10 years of solid ASIC/FPGA design and verification experience.
• Rich knowledge about ASIC design flow from specification, implementation, to verification.
• Strong in SystemC, C++/C programming.
• Solid RTL design experience using Verilog.
• Experience using HLS methodology in complex design implementation and verification is a definite asset
• Familiar with CAD tools of simulation, SystemC to RTL synthesis, RTL to gate synthesis, static timing analysis and formal verification.
• Handy in Linux script languages such as Perl, Python, Ruby or/and shell languages.
• Solid problem solving skill.
• Prior team, technical leadership or mentorship are great value added asset
• Good team player and communicator
• Basic video codec knowledge is definitely a plus.

Academic Credentials:

Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.

#LI-DC3

Requisition Number: 181589
Country: Canada Province: Ontario City: Markham
Job Function:Design

AMD is an inclusive employer dedicated to building a diverse workforce. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective provincial human rights codes throughout all stages of the recruitment and selection process. Any applicant who requires accommodation should contact AskHR@amd.com.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services.